In storage devices that utilize memory cells having select elements, to read data from a selected one of the memory cells, read voltage supplies may supply read voltages to a memory tile to generate a voltage difference across the selected memory cell that exceeds a threshold voltage level of the select element. A logic level of data stored in a memory element of the selected memory cell may depend on whether the memory element is in a high resistance state or a low resistance state. In the event that the selected memory cell is in the low resistance state, generation of the voltage difference in excess of the select element's threshold voltage level may cause a relatively large amount of current to flow through the selected memory cell. If the memory cell current is at too high of a level for too long of a period of time, the memory cell current may cause a “false write” in which the selected memory element changes its state from the low resistance state to the high resistance state, effectively causing the selected memory element to change the logic value of the data it is storing.
In addition, data stored in memory cells may be read by changing voltage levels at which selected bit lines and word lines are biased. The changes in the voltage levels may cause voltage changes in neighboring word lines and bit lines due to coupling capacitance. If the change in voltage on the selected bit lines and word lines is not performed at appropriate times or changed at appropriate rates, the change in voltage on the neighboring word lines and bit lines may create “false select” situations where the neighboring word lines and bit lines become selected. Ways to perform read operations that minimize the likelihood of false write or false selects from occurring while still aiming to perform the read operations as fast as possible may be desirable.